1. Field of the Invention
The present invention relates generally to a thin film transistor (TFT) substrate and a fabrication method thereof and more specifically, to a TFT substrate applicable to an organic light-emitting diode (OLED) display and also relates to a fabrication method of such a TFT substrate.
2. Description of the Related Art
The organic light-emitting diode (OLED) display is regarded as an advanced display because of its fast responsiveness, low power consumption, and wide view angles. The OLED display is expected to be a next-generation display that will replace the cathode ray tube (CRT) display.
An OLED display electrically excites organic components sandwiched between a pair of electrodes, and creates visual images by voltage-programming or current-programming N×M number of organic light-emitting pixels.
Methods of driving the organic light-emitting pixels include a passive matrix method and an active matrix method, the active matrix method employing a TFT. In the passive matrix method, an anode electrode and a cathode electrode are formed crossing each other, and lines are selected to drive the organic light emitting pixels. However, in the active matrix method, a TFT and a capacitor is coupled to each pixel electrode, and the light emitting pixel is driven in accordance with a voltage maintained by capacitance of the capacitor coupled to the TFT.
A typical OLED display for an active matrix method includes a display panel, a data driver, and a scan driver.
The display panel includes a plurality of data lines extending in a row direction, a plurality of scan lines extending in a column direction, and a plurality of pixel circuits. The plurality of data lines transmit data signals for an image to the pixel circuits, and the plurality of scan lines transmit selection signals to the pixel circuits, respectively. Typically, the pixel circuit includes a switching transistor, a driving transistor, a capacitor, and an OLED, and is formed at a pixel area where a data line and a scan line cross each other.
In response to the selection signal from the scan line, the switching transistor transmits a data voltage received from the data line to the driving transistor. The driving transistor determines a driving current using a data voltage applied to a gate thereof and a source voltage applied to a source thereof, and applies the determined driving current to the OLED. The capacitor maintains a gate-source voltage of the driving transistor for a predetermined time period, and the OLED emits a light corresponding to a current applied through the driving transistor.
The scan driver sequentially applies the selection signal to the scan lines, and the data driver sequentially applies a data voltage corresponding to the image signal to the plurality of data lines.
An OLED display of a system-on-panel (SOP) scheme, in which a display panel, a scan driver, and data driver are integrally formed as a single panel, is currently under serious study.
In an OLED display of the SOP scheme, peripheral circuits (such as a data driver and/or a scan driver) as well as pixel circuits are formed on the same panel. Therefore, TFTs for the pixel circuits and the peripheral circuits are formed on the panel, and the panel formed with the TFTs is called a TFT substrate.
FIG. 1 is a vertical cross-section of a conventional TFT substrate, and illustrates both an NMOS transistor and a PMOS transistor formed to provide a CMOS structure.
Conventionally, when both an NMOS transistor and a PMOS transistor are formed on a silicon substrate, a source/drain region 513a′ of the NMOS transistor and a source/drain region 513b′ of the PMOS transistor are firstly patterned, and then contact holes 519a and 519b are formed. That is, elements of the NMOS and PMOS transistors are separated by a gate insulation layer 514 and an interlayer insulating layer 518 and the contact holes 519a and 519b are respectively formed on the source/drain regions 513a′ and 513b′, respectively. In such a CMOS structure, the contact holes 519a and 519b are formed on each of the source/drain regions 513a′ and 513b′ consume excessive space in a layout design, thereby causing a deterioration of the integration level.